This invention relates generally to three phase AC drives and more specifically to drive configurations that reduce common mode voltage (CMV) that appears between a neutral point of a stator winding and the frame of a motor or other load.
FIG. 1 illustrates an exemplary AC drive 10 that is linked between a three phase AC source 12 including three supply lines 14, 16 and 18 and a three phase motor 20. AC source 12 includes a supply ground identified by label “g”. Drive 10 includes a rectifier 22, positive and negative DC buses 24 and 26, respectively, and an inverter 28. Rectifier 22 is linked between supply lines 14, 16 and 18 and DC buses 24 and 26 and converts AC voltages on lines 14, 16 and 18 to a DC potential across buses 24 and 26. To this end, rectifier 22 may be a diode bridge rectifier, a two-level PWM switching rectifier, a three-level PWM switching rectifier, etc.
Where rectifier 22 is an active switching type, rectifier switches are used to link and de-link the three supply lines 14, 16 and 18 to the positive and negative DC buses 24 and 26 in a sequence that results in DC potential across the buses. To this end, where rectifier 22 is a two-level rectifier, the switches can be controlled to assume any of eight switching states including ppp, ppn, pnp, npp, pnn, npn, nnp and nnn states where a “p” indicates that a phase is linked to positive DC bus 24 and an “n” indicates that a phase is linked to negative DC bus 26. The eight two-level rectifier switching states are illustrated in FIG. 2A along with lines between states that indicate possible transitions. Similarly, where rectifier 22 is a three level switching type, rectifier switches can be controlled to assume any of twenty-seven switching states including ppp, ppn, pnp, npp, pnn, npn, nnp, nnn, ppo, pop, opp, poo, opo, oop, oon, ono, noo, onn, non, nno, ooo, pon, pno, nop, npo, opn and onp states. Here an “o” indicates that a phase is linked to a neutral clamp point of the DC link (i.e., a midpoint between DC bus capacitors 36 and 38 (see FIG. 1)). The twenty-seven three-level switching states are illustrated in FIG. 2B along with lines indicating transitions between states.
Inverter 28 is linked between DC buses 24 and 26 and motor 20 and converts the DC to three phase AC voltages that are provided to motor 20. Here, inverter 28 is of the switching type (e.g., is a two-level PWM or three-level PWM switching inverter). Where inverter 28 is a two-level type, inverter 28 can be controlled to assume any of the eight switching states identified above with respect to the two-level rectifier. Here, however, instead of an “n” and a “p” indicating linkage of an associated supply line to negative DC bus 26 and positive DC bus 24, respectively, an “n” and a “p” indicate linkage of an associated motor phase to negative and positive DC buses 26 and 24, respectively.
Where inverter 28 is a three-level type inverter, inverter 28 can be controlled to assume any of the twenty-seven switching states identified above with respect to the three-level rectifier where an “n”, a “p” and an “o” indicate linkage of an associated motor phase to negative bus 26, to positive bus 24 and to reference point “o”, respectively.
Referring again to FIG. 2B, the twenty-seven three-level switching states can be divided into sub-sets including small, medium, zero and large voltage vector states. Small vector states include the 12 switching states with one “o” and either two “p”'s or two “n”'s and with two “o”'s and either one “p” or one “n” designations. Medium vector states include all switching states including one “o”, one “p” and one “n” designation. Zero vector states include the 3 states with all “o”, all “n” or all “p” designations. Large vector states include all states including only “n” and “p” designations and no “o”=designations.
Motor 20 includes three-phase windings that are linked together at a common node identified by label “c”. Among other components, motor 20 includes a rotor mounted on bearings for rotation within a stator where the stator is mounted to a motor frame. The frame is electrically linked to supply ground “g” (see again FIG. 1).
As known in the controls art, during switching of an AC drive, common mode voltage (CMV) is generated that appears between the motor common node c and the motor frame or supply ground g. The CMV is characterized by a peak-peak value, a step height and a fundamental frequency. If the peak-peak value surpasses a threshold, a voltage breakover can occur between the rotor bearings and the motor frame thereby causing a current to pass through the bearings to ground. Where the current is excessive, the current has been known to cause damage to the bearings thereby reducing the useful life of the bearings and other associated motor components. To this end, a large step height, high fundamental frequency, and high rate of change (dv/dt) are usually harbingers of a large current through the bearings and thus should be avoided.
Both the rectifier and inverter stages generate CMV. Referring again to FIG. 1, using neutral clamp point o of the DC link as a reference point, the CMV generated by the rectifier and inverter are vog and vco, respectively. Thus, the total CMV vcg generated by an AC drive can be expressed as:vcg=vog+vco  (1)
In the case of a diode bridge rectifier the CMV has a peak-peak value of approximately 30% of the DC bus voltage and a fundamental frequency of three times the supply frequency. Thus, where the supply frequency is 60 Hz, the fundamental frequency of the CMV is 180 Hz. In the case of a PWM converter (i.e., either a rectifier or an inverter) that uses a switching protocol that includes all possible switching states (i.e., eight and twenty-seven states for two-level and three-level converters, respectively), the CMV has a maximum peak-peak value equal to the DC bus voltage vdc and a frequency at or above the PWM switching frequency. Thus, for a drive configuration including a diode bridge rectifier and a two-level PWM inverter, the total peak-peak CMV is as high as 1.30 times the DC bus voltage vdc with a step height of 0.33 vdc. Similarly, for a drive including both a two-level PWM rectifier and a two-level PWM inverter, the total peak-peak CMV may be as high as 2.0 vdc with a step height of 0.33Vdc.
In the case of a switching type inverter or rectifier, one way to reduce CMV has been to limit the switching states of the drive components. For instance, in a first known case the inverter switches in a configuration including a diode bridge rectifier and a two-level PWM inverter have been controlled to exclude both ppp and nnn switching states. Here, the result is that the total peak-peak CMV is at or above the PWM frequency and has a value of 0.63 vdc which is much lower than the 1.30 vdc value that occurs when the ppp and nnn states are used. In a second known case the inverter switches in a configuration including a diode bridge rectifier and a three-level PWM inverter have been controlled to exclude all but medium vector switching states (i.e., pon, pno, opn, onp, nop and npo). Here the result is that the total CMV has a peak-peak value of 0.30 vdc.
Unfortunately, the configurations of each of the first and second known cases above have shortcomings. With respect to the first case where ppp and nnn switching states are excluded when controlling a two-level inverter the inverter output voltage and motor currents can have a large component at the PWM frequency and its multiples, which can increase losses in the inverter and motor.
With respect to the second case where all but medium vector switching states are excluded when controlling a three-level inverter (i.e., where large and small vector states are excluded), the large vectors cannot be used to provide maximum AC output voltage and the maximum inverter output is limited to approximately 87% of the three-phase AC input voltage. In addition, because two phase voltages have to change simultaneously while transitioning for the inverter to change from a first medium vector state to a second medium vector state, spikes occur in the CMV and some additional control scheme has to be adopted to reduce the spikes which further complicates control. Moreover, referring again to FIG. 1, the potentials above and below neutral clamp point “o” cannot be actively balanced using the limited medium vector switching states and have been known to drift during transient conditions.
Thus, it would be advantageous to have a drive configuration and control scheme wherein CMV is minimized while the level of inverter output voltage is maintained at the rated level and where other adverse control affects like unbalanced bus capacitor potentials and CMV spikes are minimized.